1. Field
This disclosure generally relates to electronic design automation. More specifically, the disclosure relates to methods and apparatuses for managing violations and error classifications during physical verification.
2. Related Art
Rapid advances in computing technology have been made possible by sophisticated verification tools which are used to verify a circuit design. Indeed, without these tools it would be almost impossible to verify complicated integrated circuits which are commonly found in today's computing devices.
To reduce design time, it is usually desirable to accurately identify errors as early as possible in the design flow. If an error is identified at a later stage, it can substantially increase the design time because a number of stages in the design flow will most likely have to be repeated for the debugged design.
Physical verification is an important stage in the design flow. In this stage, the circuit can be checked to ensure correctness for manufacturing, electrical issues, lithographic issues, etc. A physical verification tool typically identifies locations in a layout which are likely to result in manufacturing problems. The circuit designer can use this information to modify the layout so that when the circuit is taped-out, the circuit is free of manufacturing problems.
Unfortunately, conventional physical verification tools can make it very difficult to separate real errors from intended violations, especially when the tool generates a large number of violations. As a result, in conventional techniques, even after the circuit passes the physical verification stage, the circuit may still have manufacturing problems.